standard_additions -- Additions to the package "std.standard"
Use model:
use ieee_proposed.standard_additions.all;
Dependancies: None.
Notes: The functions "rising_edge" and "falling_edge" are defined in
this package. If you use "numeric_bit" they are ALSO defined in that
package, causing a conflict. The VHDL-200X-FT version of numeric_bit
has these functions commented out, as well as the "sll", "srl", "ror"
and "rol" functions which are implicit.
New types defined in this package:
- REAL_VECTOR - A vector of type real
- TIME_VECTOR - A vector of type time
- INTEGER_VECTOR - A vector of type integer
- BOOLEAN_VECTOR - a vector of type boolean
New constants defined in this package:
- SIM_RESOLUTION : TIME - returns the simulator's resolution (1 ns default)
New funcitons defined in this package:
- "maximum" and "minimum" are defined for all default datatypes
- _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
These functions reduce a bit_vector to a single bit.
Example:
or_reduce ("0101") = '1'
In VHDL-2008 syntax these will be "or".
- "vector" and "bit" operations are defined. These will perform a
boolean operation of a vector.
Example:
"1" xor "1010" = "0101";
- /??/ function is defined for "bit" ("??" operator is release)
if (/??/('1')) then -- will return a "true".
- rising_edge and falling_edge functions are defined (see Notes).
- to_string function - Converts any of the base types into a string.
Example:
assert (bv = "101") report "result was " & to_string(bv) severity note;
- to_hstring and to_ostring function (bit_vector to hex or octal string)
Please send feedback to David W. Bishop
dbishop@vhdl.org.